The present invention relates to DTCMOS circuits which are implemented in SOI. Specifically, a circuit is described having a plurality of input transistors whose threshold voltage is controlled by an early arriving logic input signal.
Dynamic threshold metal oxide semiconductor (DTMOS) devices can be fabricated on silicon-on insulator (SOI) substrates as described, for instance in U.S. Pat. No. 5,559,368. The SOI environment has offered the promise of reducing device sizes to the submicron gate level. The MOSFET devices are fabricated using a layer of semiconductor material deposited over an insulation layer of a supporting bulk wafer. The resulting structure includes a film of monocrystalline silicon on a buried layer of silicon oxide. The bulk silicon material from which the channel of the MOSFET device is formed is either grounded, or in many applications connected to the source region of the device. In accordance with the application described in the aforesaid referenced patent, the MOSFET device monocrystalline silicon film is connected to the gate of the MOSFET device to reduce the turn-on voltage (V.sub.t) when the gate voltage is high. The reduced threshold voltage V.sub.t for the device improves its performance in numerous respects. When the FET is OFF, the threshold voltage is increased reducing subthreshold leakage currents.
Applications which use DTCMOS devices provide not only the advantage of lower leakage currents while the MOSFET device is off, and lower threshold voltages when the device is on, but may also improve the speed of circuits utilizing MOSFET. The present invention is directed to one such application for improving the speed of DTCMOS logic circuits.